| 并行折叠计数器的BIST方案 |
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| 引用本文： | 梁华国,李鑫,陈田,王伟,易茂祥.并行折叠计数器的BIST方案[J].电子学报,2012,40(5):1030-1033. |
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| 作者姓名： | 梁华国 李鑫 陈田 王伟 易茂祥 |
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| 作者单位： | 1. 合肥工业大学电子科学与应用物理学院,安徽合肥23009
2. 合肥工业大学计算机与信息学院,安徽合肥23009 |
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| 基金项目： | 国家自然科学基金，博士点基金，安徽高校省级自然科学研究重点项目 |
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| 摘 要： | 本文提出了一种新的基于初始状态的并行折叠计数结构,并给出了建议的多扫描链的BIST方案.与国际上同类方法相比,该方案需要更少的测试数据存储容量、更短的测试应用时间,其平均测试应用时间是同类方案的0.265%,并且能很好地适用于传统的EDA设计流程.
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| 关 键 词： | 内建自测试 线性反馈移位寄存器 并行折叠计数器 多扫描链 测试数据压缩 |
| 收稿时间： | 2011-07-28 |
BIST Scheme of Parallel Folding Counters |
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| LIANG Hua-guo
,
LI Xin
,
CHEN Tian
,
WANG Wei
,
YI Mao-xiang.BIST Scheme of Parallel Folding Counters[J].Acta Electronica Sinica,2012,40(5):1030-1033. |
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| Authors: | LIANG Hua-guo LI Xin CHEN Tian WANG Wei YI Mao-xiang |
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| Institution: | 1(1.School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei,Anhui 23009,China;2.School of Computer and Information,Hefei University of Technology,Hefei,Anhui 23009,China) |
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| Abstract: | A new architecture of parallel folding counters is presented and a preferred BIST scheme of multiple scan chains is advised.Compared to international similar approaches,the proposed scheme needs less storage volume and shorter test application time,test application time is only as much as 0.265% of other similar scheme,and is compatible with traditional scan-based design flow. |
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| Keywords: | built-in self-test(BIST) linear feedback shift registers(LFSR) parallel folding counters multiple scan chains test data compression |
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