| 多线程非阻塞指令Cache设计 |
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| 引用本文： | 胡孔阳,陈鹏,桑红石.多线程非阻塞指令Cache设计[J].微电子学与计算机,2012,29(5):143-147. |
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| 作者姓名： | 胡孔阳 陈鹏 桑红石 |
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| 作者单位： | 华中科技大学图像识别与人工智能研究所,湖北武汉430074／华中科技大学多谱信息处理技术国家级重点实验室,湖北武汉430074 |
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| 摘 要： | 非阻塞Cache是指Cache在等待预取数据返回时,还能继续提供指令和数据.首先分析了多线程非阻塞Cache的处理器需求,然后提出其时序要求和一种实现方案.利用SystemVerilog对该方案进行RTL级建模和性能评估.仿真结果表明,该方案可以很好地应用于多线程、乱序执行处理器的指令引擎设计之中.
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| 关 键 词： | 多线程 非阻塞 Cache System Verilog 仿真模型 |
Design of a Multithreading Non-blocking Cache |
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| HU Kong-yang,CHEN Peng,SANG Hong-shi.Design of a Multithreading Non-blocking Cache[J].Microelectronics & Computer,2012,29(5):143-147. |
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| Authors: | HU Kong-yang CHEN Peng SANG Hong-shi |
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| Institution: | 1,2(1 Institute for Pattern Recognition and Artificial Intelligence,Huazhong University of Science and Technology,Wuhan 430074,China;2 National Key Laboratory of Science and Technology on Multi-spectral Information Processing,Huazhong University of Science and Technology,Wuhan 430074,China) |
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| Abstract: | Non-blocking instruction Cache is one Cache that can continue to provide instruction and data,when waiting for the prefetch data.In this paper,first analyze the processors’ demand for multithreading non-blocking cache,then put forward the timing request and the functional structure.SystemVerilog is employed to build up the simulation model of the proposed architecture and the performace evaluation.Evaluation results show that the architecture can be applied to the design of fetch engine in multithreading or out of order execution processors. |
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| Keywords: | multithreading non-blocking cache SystemVerilog simulation mode |
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