| 可配置片上网络性能评估平台 |
| |
| 引用本文： | 赵超平,王亚刚,杜慧敏,赵萍. 可配置片上网络性能评估平台[J]. 现代电子技术, 2012, 35(8): 160-164 |
| |
| 作者姓名： | 赵超平 王亚刚 杜慧敏 赵萍 |
| |
| 作者单位： | 1. 西安邮电学院电子工程学院,陕西西安,710061
2. 西安邮电学院计算机学院,陕西西安,710061 |
| |
| 基金项目： | 国家自然科学基金项目资(60976020);陕西省教育厅科研计划(2010JK833);陕西省教育厅科研计划(11JK1063) |
| |
| 摘 要： | 为了弥补目前单纯采用软件或者硬件构建NoC验证平台的一些缺陷,采用软硬件结合的设计方法实现了NoC的FPGA验证与性能评估平台。利用该平台在Xilinx Virtex 6FPGA上对基于虚通道路由器的片上网络进行了验证。实验证明该验证平台功能完善,占用硬件资源少,综合时钟频率高,评估NoC系统的效率非常高。
|
| 关 键 词： | 片上网络 验证平台 性能评估 FPGA |
Performance evaluation platform for configurable network on chip |
| |
| ZHAO Chao-Ping , WANG Ya-Gang , DU Hui-Min , ZHAO Ping. Performance evaluation platform for configurable network on chip[J]. Modern Electronic Technique, 2012, 35(8): 160-164 |
| |
| Authors: | ZHAO Chao-Ping WANG Ya-Gang DU Hui-Min ZHAO Ping |
| |
| Affiliation: | 1(1.Academy of Electronic Engineering,Xi’an University of Post and Telecommunications,Xi’an 710061,China; 2.Academy of Computer Science,Xi’an University of Post and Telecommunications,Xi’an 710061,China) |
| |
| Abstract: | To remedy the deficiencies of the network on chip(NoC) verification platform composed of software or hardware only,a performance evaluation platform for the NoC verification was designed in combination with hardware and software.A NoC based on virtual channel router was verified by this platform on the Xilinx Virtex6 FPGA.Experiment result shows that,with very little hardware resources,the verification platform possesses high efficiency to verify and evaluate the performance of NoC system. |
| |
| Keywords: | NoC verification platform performance evaluation FPGA |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
