Effect of temperature–bias annealing on the hysteresis and subthreshold behavior of multilayer MoS2 transistors

The transfer characteristics (I_D–V_G) of multilayers MoS₂ transistors with a SiO₂/Si backgate and Ni source/drain contacts have been measured on as‐prepared devices and after annealing at different temperatures (T_ann from 150 °C to 200 °C) under a positive bias ramp (V_G from 0 V to +20 V). Larger T_ann resulted in a reduced hysteresis of the I_D–V_G curves (from ～11 V in the as‐prepared sample to ～2.5 V after T_ann at 200 °C). The field effect mobility (～30 cm² V^–1 s^–1) remained almost unchanged after the annealing. On the contrary, the subthreshold characteristics changed from the common n‐type behaviour in the as‐prepared device to the appearance of a low current hole inversion branch after annealing. This latter effect indicates a modification of the Ni/MoS₂ contact that can be explained by the formation of a low density of regions with reduced Schottky barrier height (SBH) for holes embedded in a background with low SBH for electrons. Furthermore, a temperature dependent analysis of the subthreshold characteristics revealed a reduction of the interface traps density from ～9 × 10¹¹ eV^–1cm^–2in the as‐prepared device to ～2 × 10¹¹ eV^–1cm^–2after the 200 °C temperature–bias annealing, which is consistent with the observed hysteresis reduction.

Schematic representation of a back‐gated multilayer MoS₂ field effect transistor (left) and transfer characteristics (right) measured at 25 °C on an as‐prepared device and after the temperature–bias annealing at 200 °C under a positive gate bias ramp from 0 V to +20 V.