面向Saber算法的并行乘法器

随着量子计算的发展, 现有密码系统的安全性将受到严重威胁. Saber算法是抵御量子计算攻击的后量子密码方案之一, 但存在多项式商环上模乘占据运算开销过大的问题. 鉴此, 本文通过对Karatsuba算法和Schoolbook相乘方式的剖析, 提出一种面向Saber算法的并行乘法器设计方案. 该方案首先利用Karatsuba算法分解模乘运算的关键路径, 结合乘法复用和加法替换的策略减少硬件开销, 然后采用并行运算电路压缩关键运算路径时长, 最后在TSMC 65nm工艺下, 利用Modelsim和DC软件仿真验证. 结果表明 该方案运算时长为137个时钟周期, 与传统方式相比速度提升46.50%, 功耗为87.83mW, 面积为927.32×103 ?m2.

Design of parallel multiplier for Saber

With the development of the quantum computer, the security of modern cryptosystems will be placed under threat. In defending against quantum computing attacks, Saber algorithm becomes one of the schemes in the ongoing post-quantum cryptography standardization project. The bottleneck of Saber is multiplication in polynomial quotient rings, where the multiplication occupies high costs in computation operation. In this paper, a parallel multiplier for Saber is proposed, which is based on analysis of Karatsuba and Schoolbook. Firstly, disassembling the calculated path of polynomial modulo multiplication is carried out by the Karatsuba algorithm, whereby a strategy of combining multiplication reused with addition superseding multiplication is utilized to reduce hardware overhead. Secondly, the critical path is compressed by a parallel structure. Finally, in the TSMC 65nm process, analysis is conducted using the tools of Modelsim and DC. The results indicate that the designed scheme accomplishes 137 clock cycles’ critical path of an operation, improving 46.5% in speed performance as compared with the conventional method, the power consumption is 87.83mW and the area overhead is 927.32×103 ?m2.