分段式高性能近似加法器设计

利用近似加法器输出误差与输出位权重有关的特点, 提出了一种分段式近似加法器结构. 该近似加法器由三部分组成, 权重高部分由精确加法器构成, 权重低部分的输出被置为全1, 而中间部分由二输入OR门代替全加器. 提出的近似加法器与精确行波进位加法器相比, 在面积、功耗、功耗延迟积和面积延迟积分别改善了约43%、57%、85%和81%, 与已有的近似加法器相比, 总体性能也有明显提升.

Design of segmenting high performance approximate adder

Taking advantage of the feature that the error distance of an approximate adder is closely related to the weight of the corresponding bit with error output, a segmented approximate adder structure is proposed in this paper. The approximate adder includes three parts the part with the highest weight being composed of an accurate adder, the part with the lowest weight having each output set to 1, and the middle part consisting of two-input OR gates instead of the full adders. Compared with the ripple carry adder, the proposed approximate adder attains significant improvements in area, power consumption, power delay product, and area delay product by about 43%, 57%, 85%, and 81% respectively. Compared to the existing approximate adders, the overall performance is also improved significantly.