高密度Si基半导体电容器的性能及其制作

随着各种混合信号电路的性能和集成度的迅速提高以及对电路模块和元器件小型化的需要,集成无源技术成为一种取代分立无源器件以达到小型化的解决方案。鉴于电容器被广泛用于滤波、调谐和电源回路退耦等各种板级集成封装中,采用Si MEMS工艺,在半导体表面深刻蚀三维(3D)图形以增大有效表面积,制作了一种高电容密度的半导体pn结退耦电容器,并分析研究了其主要制成工艺和性能。结果显示,所制作的电容器的电容密度达8～12nF/mm2,相比无表面三维刻蚀图形的半导体电容器电容密度增大了10倍以上,退耦频率范围为10kHz～3.2GHz,可用于中低频率较大范围内的退耦。

Fabrication and Property of High Density Silicon-Based Semiconductor Capacitors

With the rapidly improvement of the performance and integration of the mixed-signal circuits and the growing miniaturization requirement of modules and components in electronic applications,the integrated passive technology becomes a potentially attractive solution to replace discrete passive devices.Capacitors are widely used in various board level integrated packages,including filtering,tuning and power circuit decoupling.Fabrication process and properties of the high density semiconductor pn junction decoupling capacitor for high frequency and high speed fields were investigated with silicon MEMS process based on the deep etching 3D patterns on the semiconductor surface.The results indicate that the capacitance density reaches 12 nF/mm2 which is 10 times greater than that of the normal plane semiconductor capacitor,and the range of decoupling frequency is 10 kHz-3.2 GHz,proving the outstanding reliability of the capacitor fabrication process.Thus the process is suitable for a wide rang of medium-and low-frequency decoupling.