Diagnosis of Boards for Realistic Interconnect Shorts

Original algorithms and tools for generating diagnostic test setsfor board interconnect shorts, and assessing their diagnostic resolution areproposed. The test sets are derived from a representation of realisticshorts, extracted from the board layout. Diagnostic resolution isstatistically evaluated by simulating diagnosis of a sample of realisticshorts. The overall methodology is based on a new theoretical framework thataccounts for the probabilities of shorts, according to their multiplicityand possible logic behaviour. Results on real board layouts show that,compared to the traditional schemes, our test sets have higher diagnosticresolution, shorter test vectors, and can be produced efficiently.