Design of robust signal and clock networks

As technology scales down into the nanometer region new design challenges emerge. Wire delays become the performance bottleneck in VLSI circuits. Copper is introduced as new wiring material because of its low sheet resistivity, hence low signal propagation delay. The main defect mechanism shifts from shorts to opens due to the different manufacturing process for copper wires. Open defects limit functional yield. Parametric yield decreases because of timing uncertainties emerging from manufacturing variation. Clock skew variation becomes critical because it may shorten the cycle length of the critical path. The variation of signal nets has to be considered simultaneously avoiding overly pessimistic designs. Design techniques which reduce the variation of design parameters avoid over design and increase parametric yield. Whereas tree topologies have been applied due to their minimal wire length, the application of generic routing graphs provides multiple paths to specific sinks. Multiple paths from source to sink increase the robustness against open defects and smoothes the effect of variation. New design techniques applying loops in VLSI wiring networks are the topic of this abstract. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)