增强工艺偏差容忍度的带隙基准电压源设计

随着CMOS工艺特征尺寸的减小，带隙基准电压源在制造过程中因器件失配和工艺波动易导致实际输出电压和目标值发生偏离，降低芯片成品率.为此提出将Pelgrom失配模型引入电路设计中，分别从器件参数、电路结构、版图布局三方面对亚微米级的电路进行工艺偏差优化.基于华润上华（CSMC）0.5 μm工艺以及Hspice软件仿真，显示基准源输出电压为1.232 54 V，偏差小于5 mV.流片测试结果表明，应用此设计的三通道LED驱动控制芯片成品率达到96.8%，输出电流达到（18±0.5）mA的芯片占99.6%以上.

Bandgap voltage reference design with enhanced tolerance of process variations

As the feature size of CMOS technology is scaled down, devices mismatch and process tolerance will lead to deviation in bandgap reference voltage, which significantly impacts manufacturing cost by decreasing yield. Based on the Pelgrom's mismatch model, this paper proposes a design methodology from three aspects: parameters, schematic and layout. Hspice simulation result shows that the output of the bandgap reference circuit is(1.232 54±0.005)V in CSMC 0.5 μm technology. Applying this design in 3 channels LED driver chips, the test results indicate that the yield reaches 96.8%, while the chips that meet the output current requirements of(18±0.5) mA account for above 99.6%.