| 基于FPGA的RS译码器实现 |
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| 引用本文： | 何涌,潘泽友.基于FPGA的RS译码器实现[J].通信技术,2007,40(11):30-32. |
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| 作者姓名： | 何涌 潘泽友 |
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| 作者单位： | 1. 西南科技大学,信息工程学院,四川,绵阳,621010
2. 中国工程物理研究院,四川,绵阳,621010 |
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| 摘 要： | RS码以强大的纠错能力得到广泛的应用，以往的译码器的硬件实现总是很复杂，资源利用较多，译码周期也较长．文中采用Blahut算法，先用MATLAB进行了软件仿真，并验证了算法的正确性，然后用FPGA实现了RS（31，15）译码器的设计．在硬件设计中优化了原来的电路结构，减少了一个迭代周期，从而一定程度上提高了译码器的译码速度，而FPGA实现复杂度也较低．
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| 关 键 词： | RS码 GF域 Blahut算法 MATLAB仿真 FPGA |
| 文章编号： | 1002-0802（2007）11-0030-03 |
| 收稿时间： | 2007-05-08 |
| 修稿时间： | 2007年5月8日 |
Implementation of RS Decoder Based on FPGA |
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| HE Yong,PAN Ze-you.Implementation of RS Decoder Based on FPGA[J].Communications Technology,2007,40(11):30-32. |
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| Authors: | HE Yong PAN Ze-you |
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| Abstract: | RS code is widely used because of its very strong correcting ability.Many RS decoders have been improved,but they are too complexity and occupies a lot of hardware resources.In other hand,it takes a long period to decode a code.In this paper,Blahut algorithm is introduced.The algorithm is first simulated by MATLAB.The simulation shows that the algorithm is right.Then,the RS(31,15) decoder is implemented by using the algorithm on a FPGA chip.The decoder structure is modified in some sense to decrease delay.The structure is easy for implementation based on FPGA. |
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| Keywords: | RS code Galois field Blahut algorithm MATLAB simulation FPGA |
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