Energy-Efficient Double-Edge Triggered Flip-Flop |
| |
Authors: | Chua-Chin Wang Gang-Neng Sung Ming-Kai Chang Ying-Yu Shen |
| |
Institution: | (1) Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan |
| |
Abstract: | This paper presents a novel design for a double-edge triggered flip-flop (DETFF). A detailed analysis of the transistors used
in the DETFF is carried out to determine the critical path. Therefore, the proposed DETFF employs low-V
th transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-V
th transistors can be resolved simultaneously. Therefore, the proposed DETFF fully utilizes the multi-V
th scheme provided by advanced CMOS processes without suffering from a large area penalty, slow clock frequency, and poor noise
immunity. The proposed design is implemented using a typical 0.18-μm 1P6M CMOS process. The measurement results reveal that
the proposed DETFF reduce the power-delay product by at lease 25% (i.e., dissipated energy). |
| |
Keywords: | |
本文献已被 SpringerLink 等数据库收录! |
|