A wideband low power low phase noise dual-modulus prescaler |
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Authors: | Lei Xuemei Wang Zhigong Wang Keping |
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Institution: | 1. Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China;Inner Mongolia University, Hohhot 010021, China 2. Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China |
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Abstract: | This paper describes a novel divide-by-32/33 dual-modulus prescaler (DMP). Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18-μm CMOS process of SMIC. The measured results show that the DMP's operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is-134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57×30μm2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications. |
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Keywords: | dual-modulus prescaler wideband low power low phase noise frequency synthesizer multi-standard radio |
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