| On-Chip Multi-Giga Bit Cycle-to-Cycle Jitter Measurement Circuit |
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| 作者姓名： | 张靖恺 李崇仁 田超 余菲 |
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| 作者单位： | Institute of Microelectronics Peking University Shenzhen Graduate School，Department of Electronics Engineering，National Chiao Tung University，Institute of Microelectronics，Peking University Shenzhen Graduate School，Institute of Microelectronics，Peking University Shenzhen Graduate School，Shenzhen 518055，China，Hsin Chu Taiwan，China，Shenzhen 518055，China，Shenzhen 518055，China |
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| 摘 要： | This paper presents an on-chip measurement circuit to measure multi-giga bit cycle-to-cycle jitter based on the vernier oscillator (VO), which is inherited from the famous vernier delay line. The calibration method is also given. The circuit adopts a differential digital controlled delay element, which makes the circuit flexible in adjusting the measurement resolution, and a highly sensitive phase capturer, which makes the circuit able to measure jitters in pico-second range. The parallel structure makes it possible to measure consecutive cycle-to-cycle jitters. The performance of the circuit was verified via simulation with SMIC 0.18 μm process. During simulation under the clock with the period of 750 ps, the error between the measured RMS jitter and the theoretical RMS jitter was just 2.79 ps. Monte Carlo analysis was also conducted. With more advanced technology, the circuit can work better. This new structure can be implemented in chips as a built-in self-test IP core for testing jitter of PLL or other clocks.
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On-Chip Multi-Giga Bit Cycle-to-Cycle Jitter Measurement Circuit |
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| ZHANG Jingkai,Chung Len Lee,TIAN Chao,YU Fei.On-Chip Multi-Giga Bit Cycle-to-Cycle Jitter Measurement Circuit[J].Tsinghua Science and Technology,2007,12(Z1):1-7. |
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| Authors: | ZHANG Jingkai Chung Len Lee TIAN Chao YU Fei |
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| Abstract: | This paper presents an on-chip measurement circuit to measure multi-giga bit cycle-to-cycle jitter based on the vernier occillator (VO), which is inherited from the famous vernier delay line. The calibration method is also given. The circuit adopts a differential digital controlled delay element, which makes the circuit flexible in adjusting the measurement resolution, and a highly sensitive phase capturer, which makes the circuit able to measure jitters in pico-second range. The parallel structure makes it possible to measure consecutive cycle-to-cycle jitters. The performance of the circuit was verified via simulation with SMIC 0.18 urn process. During simulation under the clock with the period of 750 ps, the error between the measured RMS jitter and the theoretical RMS jitter was just 2.79 ps. Monte Carlo analysis was also conducted. With more advanced technology, the circuit can work better. This new structure can be implemented in chips as a built-in self-test IP core for testing jitter of PLL or other clocks. |
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| Keywords: | jitter measurement cycle-to-cycle jitter vernier delay line vernier oscillator |
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