Memory LSI reliability

Large-scale integrated (LSI) memory circuit reliability is reviewed. Reliability of large-scale integrated memory circuits is discussed. The major physical mechanisms for failures in memory LSIs and measures to counter these failures are reviewed. Fault-tolerant techniques, divided into the spare row/column line substitution. (SLS) technique and the on-chip error-correcting code (ECC) technique, developed to overcome hard and soft failures are described. Design approaches for realizing high performance and high reliability are also discussed