| 1.25～3.125 Gb/s连续数据速率CDR设计 |
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| 引用本文： | 矫逸书,周玉梅,蒋见花,吴斌.1.25～3.125 Gb/s连续数据速率CDR设计[J].半导体技术,2010,35(11):1111-1115. |
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| 作者姓名： | 矫逸书 周玉梅 蒋见花 吴斌 |
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| 作者单位： | 中国科学院微电子研究所,北京,100029;中国科学院微电子研究所,北京,100029;中国科学院微电子研究所,北京,100029;中国科学院微电子研究所,北京,100029 |
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| 基金项目： | 国家科技重大专项资助项目 |
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| 摘 要： | 设计了一款工作速率为1.25～3.125 Gb/s的连续可调时钟数据恢复(CDR)电路,可以满足多种通信标准的设计需求.CDR采用相位插值型双环路结构,使系统可以根据应用需求对抖动抑制和相位跟踪能力独立进行优化.针对低功耗和低噪声的需求,提出一种新型半速率采样判决电路,利用电流共享和节点电容充放电技术,数据速率为3.125 Gb/s时,仅需要消耗50 μA电流.芯片采用0.13 μm工艺流片验证,面积0.42 m㎡,功耗98 mw,测试结果表明,时钟数据恢复电路接收PRBS7序列时,误码率小于10-12.
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| 关 键 词： | 时钟数据恢复 锁相环 高速采样器 判决电路 采样电路 |
Design of 1.25-3.125 Gb/s Continuous-Rate CDR Circuits |
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| Jiao Yishu,Zhou Yumei,Jiang Jianhua,Wu Bin.Design of 1.25-3.125 Gb/s Continuous-Rate CDR Circuits[J].Semiconductor Technology,2010,35(11):1111-1115. |
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| Authors: | Jiao Yishu Zhou Yumei Jiang Jianhua Wu Bin |
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| Institution: | Jiao Yishu,Zhou Yumei,Jiang Jianhua,Wu Bin(Institute of Microelectronics of Chinese Academy of Science,Beijing 100029,China) |
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| Abstract: | A continuously variable clock and data recovery(CDR) circuit operating at 1.25-3.125 Gb/s was introduced,which was applicable to the design requirements of various communication standards.The CDR with the phase interpolator based on the dual loop clock could optimize the jitter suppression and phase tracking.A new half-rate sampling and decision circuit was proposed to optimize the low power consumption and low noise.Using a current sharing and node capacitor chargedischarge technique,when the sample rate i... |
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| Keywords: | clock and data recovery PLL high speed sampler decision circuit sample circuit |
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