Sigma-Delta 调制器的建模、分析和设计

This paper introduces a new method for SC sigma–delta modulator modeling. It studies the integrator's different equivalent circuits in the integrating and sampling phases. This model uses the OP-AMP input pair's tail current (I₀) and overdrive voltage (v_on) as variables. The modulator's static and dynamic errors are analyzed. A group of optimized I₀ and v_on for maximum SNR and power × area ratio can be obtained through this model. As examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively, which verifies the modeling and design criteria.