| 80位并行3D-DCT硬件核解决方案 |
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| 引用本文： | 罗玉平,尹社广,施业斌,陈海涛,代镭.80位并行3D-DCT硬件核解决方案[J].中国科学技术大学学报,2003,33(1):45-51. |
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| 作者姓名： | 罗玉平 尹社广 施业斌 陈海涛 代镭 |
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| 作者单位： | 中国科学技术大学电子科学与技术系,安徽,合肥,230026 |
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| 基金项目： | 国家 8 63资助项目 (863 3 17 0 3 0 1 0 5 2 0) |
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| 摘 要： | 提出一种使用三维离散余弦变换 ( 3D DCT)对运动图像进行压缩解压的新算法 .在此算法的基础上构造了一个 80位 3D DCT硬件核 ,通过并行连乘连加运算加快计算速度、三维转置存储体消除矩阵转置耗时、中间寄存器消除中间计算结果的存取时间等综合手段 ,达到高速处理目的 .FPGA实现的时序模拟表明 ,采用这种算法可以对现有制式的电视图像进行实时压解处理 .
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| 关 键 词： | 三维离散余弦变换 80位并行乘加核 实时压缩 FPGA |
| 文章编号： | 0253-2778(2003)01-0045-07 |
| 修稿时间： | 2001年9月20日 |
80 Bit-Paralleled Three-Dimensional DCT Core Solution |
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| LUO Yu-ping,YIN She-guang,SHI Ye-bin,CHEN Hai-tao,DAI Lei.80 Bit-Paralleled Three-Dimensional DCT Core Solution[J].Journal of University of Science and Technology of China,2003,33(1):45-51. |
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| Authors: | LUO Yu-ping YIN She-guang SHI Ye-bin CHEN Hai-tao DAI Lei |
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| Abstract: | This paper proposes a new algorithm on motion pictu re compression and decompression using Three-dimensional Discrete Cosine Transfor m. The algorithm not only emphasizes reducing computation but also helpful with hardware implementation. Based on this approach, an 80 bit-parallelled 3D-DC T hardware is developed, which uses parallel multiplication to accelerate comput ation ,three-dimensinal transposition memory to remove the time consumption of transposition operation and temporary register to reduce the time of accessing i ntermediate values. FPGA simulations show that real time video 3D-DCT compressi on can be completed by using the hardware core. |
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| Keywords: | D-DCT 80 bit-paralleled multiplication and add core real time compression and decompression FPGA |
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