Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment |
| |
| Affiliation: | 1. College of Science, China University of Petroleum (East China), Qingdao, Shandong 266580, PR China;2. Institute of Microelectronics & Department of Electrical Engineering, Advanced Optoelectronic Technology Center, Center for Micro/Nano Science and Technology, National Cheng Kung University, Tainan 70101, Taiwan |
| |
| Abstract: | A decoupled plasma nitridation (DPN) with post nitridation annealing (PNA) treatment method was introduced to improve the performances of MOS devices with high-k (HK)-last/gate-last integration scheme and chemical oxide interface layer (IL). By introducing N to form HfSiON, it was found that DPN + PNA treatments could provide smaller equivalent oxide thickness (EOT) for both nMOS and pMOS devices. It was also found that we could achieve the best overall device performance for the HK-last/gate-last integration scheme with a chemical oxide IL by introducing nitrogen gas with low percentage content during DPN followed by high temperature PNA. |
| |
| Keywords: | Interfacial layer (IL) EOT DPN PNA |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
