Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) |
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| Institution: | 1. School of Electronics Engineering, Kyungpook National University, Daegu 702-701, Republic of Korea;2. Department of IT Convergence Engineering, Gachon University, Gyeonggi-do 461-701, Republic of Korea;3. Department of Electronic Engineering, Gachon University, Gyeonggi-do 461-701, Republic of Korea |
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| Abstract: | In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III–V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (tepi) and height of source region (Hsource) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (Ion) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (Vt) of 0.1 V, current gain cut-off frequency (fT) of 12 GHz, and maximum oscillation frequency (fmax) of 283 GHz. |
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| Keywords: | Gate-all-around (GAA) Tunneling field-effect transistor (TFET) Physical design Design optimization Low-power (LP) |
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