An offset cancellation technique for comparators using body-voltage trimming

A novel offset cancellation technique based on body-voltage trimming is presented to be used in the comparators employed in high-speed analog-to-digital converters (ADCs) such as Flash ADCs. The proposed offset cancellation is achieved by body-voltage adjustment using a low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output or complicated digital calibration scheme. The accuracy of the proposed technique is higher than its digital calibration counterparts due to its analog nature. Simulation results in a 1.8?V 0.18???m CMOS technology show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 36.2 to 7.1?mV operating at 1?GHz with only 32???W of power dissipation in the offset cancellation circuit.