A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition |
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Institution: | 1. Institute of Electronics, Chinese Academy of Sciences, Beijing, 100190, China;2. Beijing Key Laboratory of Big Data Technology for Food Safety, Beijing Technology and Business University, Beijing, 100048, China;3. University of Chinese Academy of Sciences, Beijing, 100049, China;4. China Academy of Electronics and Information Technology, Beijing, 100041, China;5. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China;1. School of Science, Shandong Jianzhu University, Jinan 250101, China;2. FEMTO-ST Institute (UMR 6174 CNRS), Univ. Bourgogne Franche-Comté (UBFC), Belfort 90000, France;1. Department of Engineering, University of Perugia, Terni, Italy;2. DIEM, University of Salerno, Fisciano (SA), Italy;3. DIMES, University of Calabria, Rende (CS), Italy |
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Abstract: | This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm2. The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported. |
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Keywords: | Floating-point Fast fourier transform (FFT) Mixed-radix Multi-path delay feedback (MDF) Binary-tree decomposition Twiddle factor Fused FP arithmetic unit |
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