CMOS集成电路闩锁效应抑制技术

闩锁效应是CMOS集成电路在实际应用中失效的主要原因之一,而且随着器件特征尺寸越来越小,使得CMOS电路结构中的闩锁效应日益突出。文章以P阱CMOS反相器为例,从CMOS集成电路的工艺结构出发,采用可控硅等效电路模型,较为详细地分析了闩锁效应的形成机理,给出了闩锁效应产生的三个基本条件,并从版图设计和工艺设计两方面总结了几种抑制闩锁效应的关键技术。

Overview on the Prevention of Latch-up Effect in CMOS IC

Latch-up effect is one of main cause that CMOS IC becomes invalid in application, and as device channel length becomes smaller and smaller, Latch-up effect in CMOS structure is stand out increasingly. Based on CMOS inverter in P-well, the structure of CMOS IC are presented.SCR equivalent circuit model is took to analyze the mechanism of latch-up in detail, gives three main conditions that latch-up becomes and sums up several kinds of key technology in prevention from layout and process.