| 基于PowerPC603e通用处理模块的设计与实现 |
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| 引用本文： | 王岚. 基于PowerPC603e通用处理模块的设计与实现[J]. 淮阴师范学院学报(自然科学版), 2009, 8(4): 297-301,305 |
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| 作者姓名： | 王岚 |
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| 作者单位： | 南京信息职业技术学院,信息服务学院,江苏,南京,210046 |
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| 摘 要： | Power PC系列处理器是高性能、低功耗的32位嵌入式处理器.Power PC系列处理器在嵌入式系统中得到了广泛的应用,文章简要介绍了Power PC603e处理器的特点,详细阐述了基于Power PC603e的通用处理模块的组成、原理以及60x总线存储器控制器在FPGA上的设计与主要时序的产生.此FPGA控制器可提供60x总线与多种类型的SRAM、FLASH和I/0的接口,已在嵌入式系统的设计中得到了应用和验证.
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| 关 键 词： | 精简指令集计算机 通用模块 猝发操作 |
Design and Implementation of an Universal Processing Module Based on PowerPC603e |
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| WANG Lan. Design and Implementation of an Universal Processing Module Based on PowerPC603e[J]. Journal of Huaiyin Teachers College(Natrual Science Edition), 2009, 8(4): 297-301,305 |
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| Authors: | WANG Lan |
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| Abstract: | PowerPC serial CPUs are high-performance,low-power 32-bit embedded processors.PowerPC serial CPUs are widely used in embedded systems.The characteristic of PowerPC603e CPU is briefly introduced in the paper.Details of the combination,the principle,the 60x bus memory controller's design on FPGA and the main timing generation of universal processing module based on PowerPC603e are describes.This FPGA controller can provide interfaces to several types of SRAM,FLASH and I/0.It has been applied and verified in a embedded system. |
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| Keywords: | reduced instruction set computer(RISC) universal module burst operation |
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