A silicon stress-sensitive unijunction transistor

The performance of a silicon stress-sensitive unijunction transistor is investigated. The transistor is classed as a stress-sensitive semiconductor lateral bipolar device with an S-type input (emitter) I-V characteristic. The optimal layout of the device and its basic parameters are determined. The device can serve as a basis for designing relaxation oscillators with the physically integrated function of mechanical stress-to-signal frequency conversion at the output.