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Parallel BIST architecture for CAMs |
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| Authors: | Yong-Seok Kang Jong-Cheol Lee Sungho Kang |
| Institution: | Dept. of Electr. Eng., Yonsei Univ., Seoul; |
| Abstract: | A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved |
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