一种级间运放共享的MASH结构Σ-Δ调制器

基于55 nm CMOS工艺，设计了一种级间运放共享的级联噪声整形(MASH)结构Σ-Δ调制器。采用2-2 MASH结构对调制器参数进行了设计。对经典结构的开关电容积分器进行了改进，并应用到调制器电路的设计中，实现了两级调制器之间的运放共享，在达到高精度的同时减少了运放的数量，显著降低了MASH结构调制器的功耗。仿真结果表明，在3.3 V电源电压下，调制器信噪失真比为111.7 dB,无杂散动态范围为113.6 dB,整体功耗为16.84 mW。

A MASH Structure Interstage Op-Amp Sharing Σ-Δ Modulator

A multi-stage noise-shaping (MASH) structure interstage op-amp sharing Σ-Δ modulator was designed in a 55 nm CMOS process. A 2-2 MASH structure was used to design the modulator parameters. An improvement had been made to the classical switched-capacitor integrator and applied to the design of the modulator circuit, realizing the sharing of op-amps between the two stages of the modulator, reducing the number of op-amps while achieving high precision, and significantly decreasing the power consumption of the MASH structure modulator. Simulation results show that at a supply voltage of 3.3 V, the modulator have a signal-to-noise-and-distortion ratio of 111.7 dB, a spurious-free dynamic range of 113.6 dB, and a total power consumption of 16.84 mW.