一种快速同步的时钟数据恢复电路的设计实现

时钟数据恢复(CDR)电路是通信传输设备中的重要部分,对于突发式的接收,基于锁相环的传统的CDR往往不能满足其快速同步的要求.对此,文章采用过采样方式基于FPGA设计实现了一种全数字化的155.52Mb/s下的CDR电路.理论分析、仿真和实验测试结果表明,该CDR电路可以有效地对相位变化实现快速同步,有很大的捕捉范围,且系统较锁相环便于集成.

Design and implementation of a rapid synchronous clock and data recovery circuit

Clock and data recovery circuit is an important part of the synchronous optical communication device. According to the burst mode receiver, oversampling CDR can be applied as mentioned since traditional phase locked loop (PLL) always could not satisfy the restriction of the rapid synchronization. This method is based on multi-phase sampling and digital post-processing. The operating principles, the acquisition performance and bit error performance analysis, and experiment results are given to illustrate that the approach is more effective and robust towards synchronize phase variation and has a wider catching range. Moreover, this technique is completely digital and can be implemented in FPGA for 155.52Mb/s CDR.