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IC设计技术中的IP核互连
引用本文:朱运航,黄秀亮.IC设计技术中的IP核互连[J].中国集成电路,2008,17(10):43-46.
作者姓名:朱运航  黄秀亮
作者单位:湖南信息职业技术学院信息工程系,湖南,长沙,410200
摘    要:随着IC设计复杂度的不断提高,在SoC中集成的IP核越来越多,基于片上总线的SOC设计技术解决了大规模集成电路的设计难点,但是片上总线的应用带来了可扩展性差、平均通信效率低等问题。近几年来,将英特网络中分层互连的思想引入到SOC设计中IP核的互连上来,提出了全新的集成电路体系结构——片上网络(NOC),NOC从多处理体系结构、消除时钟树以节省资源、实现并行通信等几个方面,展示了优于总线结构的本质和特性,成功地解决了SOC设计中存在的问题。

关 键 词:集成电路  IP  片上系统  片上总线  片上网络

IP Core Interconnection in IC Design Technology
ZHU Yun-hang,HUANG Xiu-liang.IP Core Interconnection in IC Design Technology[J].China Integrated Circuit,2008,17(10):43-46.
Authors:ZHU Yun-hang  HUANG Xiu-liang
Institution:(Department of Information Engineering, Hunan Information College, Changsha 410200, China)
Abstract:With the improvement of complexity in IC design,IP reuse has become one of the main solution in SOC design.SOC design technology based on bus has some disadvantages,such as poor scalability and lower communication efficiency,etc.In recent years,a new architecture NOC is proposed,in which bus interconnection for chip is replaced by computer network interconncetion.And it will overcome the disadvantages of SOC design thoroughly and become a mainstream design technology for the next generation intergrated circuit.
Keywords:IC  IP  SOC  Bus on chip  Network on chip
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