Fault-Tolerant Design of a Shift Register at the Nanoscale Based on Quantum-dot Cellular Automata

Quantum-dot Cellular Automata (QCA) as a novel technology in the nanometer scale has been considered as one of the substitutes to CMOS technology. The QCA helps to create faster computers with lower power consumption. On the other hand, a shift register as one of the most important logical circuit in the digital systems consists of a line of latches. Also, the QCA-based designs have more advantages compared to the conventional CMOS designs. However, some deposition defects are possible to occur in the QCA-based designs, which have necessitated the fault-tolerant structures. Therefore, this paper aims to design an optimized 2-bit universal shift register based on QCA technology through the optimized multiplexer and D flip-flop. This paper studies the functionality and the fault tolerance of the proposed universal shift register in the presence of the QCA deposition faults. The structure of the 2-bit universal register is extendable to 4-bit, 8-bit and higher. The proposed design has better performance regarding fault tolerant, complexity and area consumption compared to the current designs based on the achieved results via QCADesigner.