| 一种基于二进制搜索每级输出2位的6-bit 230-MS/s单通道异步逐次逼近模数转换器 |
| |
| 引用本文： | 韩雪,魏琦,杨华中,汪蕙.一种基于二进制搜索每级输出2位的6-bit 230-MS/s单通道异步逐次逼近模数转换器[J].半导体学报,2014,35(7):075005-6. |
| |
| 作者姓名： | 韩雪 魏琦 杨华中 汪蕙 |
| |
| 基金项目： | Project supported by the National Science Foundation for Young Scientists of China （No. 61306029） and the National High Technology Research and Development Program of China （No. 2013AA014103）. |
| |
| 摘 要： | This paper proposes a single channel, 6-bit 230-MS/s asynchronous successive approximation register analog-to-digital converter （ADC） in an SMIC 65 nm CMOS technology. Through adopting the modified 2 bits/stage asynchronous control logic, the presented ADC actualizes a peak 40.90-dB spurious-free dynamic range and 29.05-dB signal-to-noise and distortion ratio at 230-MS/s sampling rate. Utilizing the dynamic comparator without the preamplifier, this work attains low-power design with only 0.93 mW power consumption and accomplishes a figure of merit of 174.67 fJ/step at 1 V supply voltage.
|
| 关 键 词： | ADC MS 异步 单声道 SAR 低功耗设计 CMOS技术 数字转换器 |
A single channel, 6-bit 230-MS/s asynchronous SAR ADC based on 2 bits/stage |
| |
| Han Xue,Wei Qi,Yang Huazhong and Wang Hui.A single channel, 6-bit 230-MS/s asynchronous SAR ADC based on 2 bits/stage[J].Chinese Journal of Semiconductors,2014,35(7):075005-6. |
| |
| Authors: | Han Xue Wei Qi Yang Huazhong and Wang Hui |
| |
| Institution: | Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China;Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China;Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China;Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China |
| |
| Abstract: | This paper proposes a single channel, 6-bit 230-MS/s asynchronous successive approximation register analog-to-digital converter (ADC) in an SMIC 65 nm CMOS technology. Through adopting the modified 2 bits/stage asynchronous control logic, the presented ADC actualizes a peak 40.90-dB spurious-free dynamic range and 29.05-dB signal-to-noise and distortion ratio at 230-MS/s sampling rate. Utilizing the dynamic comparator without the preamplifier, this work attains low-power design with only 0.93 mW power consumption and accomplishes a figure of merit of 174.67 fJ/step at 1 V supply voltage. |
| |
| Keywords: | analog-to-digital converter successive approximation register asynchronous control logic 2 bits per stage |
| 本文献已被 维普 万方数据 等数据库收录！ |
| 点击此处可从《半导体学报》浏览原始摘要信息 |
| 点击此处可从《半导体学报》下载免费的PDF全文 |
|
