| 基于March C＋算法的SRAMBIST设计 |
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| 引用本文： | 张志超,侯立刚,吴武臣.基于March C＋算法的SRAMBIST设计[J].现代电子技术,2011,34(10):149-151. |
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| 作者姓名： | 张志超 侯立刚 吴武臣 |
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| 作者单位： | 北京工业大学集成电路与系统集成实验室,北京,100124 |
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| 基金项目： | 国家自然科学基金资助项目，北京工业大学博士启动基金资助项目 |
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| 摘 要： | 为了增加存储器测试的可控性和可观测性，减少存储器测试的时间和成本开销，在此针对LEON处理器中的32位宽的SRAM进行BIST设计。采用MarchC＋算法，讨论了SRAM的故障模型及BIST的实现。设计的BIST电路可以与系统很好的相连，并且仅增加很少的输入／输出端口。仿真结果证明，BIST的电路的加入在不影响面积开销的同时，能够达到很好的故障覆盖率。
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| 关 键 词： | SRAM BIST March C＋算法 故障模型 |
SRAM BIST Design Based on March C+ Algorithm |
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| ZHANG Zhi-chao,HOU Li-gang,WU Wu-chen.SRAM BIST Design Based on March C+ Algorithm[J].Modern Electronic Technique,2011,34(10):149-151. |
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| Authors: | ZHANG Zhi-chao HOU Li-gang WU Wu-chen |
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| Institution: | ZHANG Zhi-chao,HOU Li-gang,WU Wu-chen(VLSI Lab of BJUT,Beijing 100124,China) |
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| Abstract: | In order to increase controllability and observability in memory testing and to reduce the testing time,a BIST design based on March C+ algorithm for a 32-bits SRAM in LEON processor is proposed,in which SRAM fault model and BIST implementation are discussed.The designed BIST circuit can well connect with system,and only increase few I/O ports.Simulation results prove that the BIST design has good fault coverage without increasing chip area. |
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| Keywords: | SRAM BIST March C algorithm fault model |
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