A compact low-power UHF RFID tag

In this paper, the design of an ultra-low-power UHF RFID tag is introduced. The system architecture and the communication protocols are chosen to operate with the minimum requirements possible from the RFID tag. By moving most of system functionality to the RFID reader side, the circuit requirements of the RFID tag circuits are relaxed. Supply voltages for both analog and digital parts are chosen carefully for minimum power consumption. The RFID tag is designed in standard digital 0.13 μm CMOS technology. Simulations results of the main blocks are shown. The power consumption of the chip is only 1 μW, and the chip area is only 0.14 mm×0.23 mm.