| Abstract: | The capabilities to study the geometrical construction of silicon devices by the technique of the electron beam induced current (EBIC) are reviewed with particular emphasis to the 2-dimensional determination of dopant boundaries (p-n junctions) including a discussion of demands for such investigations from a microelectronic point of view. The investigations of buried layers and MOS short-channel transistors are outlined. As a substantial topic the preparation of electrically stable surfaces at cleaved samples is discussed and an example of the possibility of cross-sectional analysis for junction delination is briefly given. |
