| 基于FPGA的高速RS编解码器设计与实现 |
| |
| 引用本文： | 顾艳丽,周洪敏.基于FPGA的高速RS编解码器设计与实现[J].信息技术,2008,32(6). |
| |
| 作者姓名： | 顾艳丽 周洪敏 |
| |
| 作者单位： | 南京邮电大学光电工程学院,南京,210003 |
| |
| 摘 要： | 详细介绍了RS( 255,191)编解码器的设计,按照自上而下的设计流程给出了算法的FPGA实现.根据编解码器的不同特点, 采用不同方法实现GF(28)乘法器.编码器采用并行结构、解码器采用并行无逆的BM算法实现关键模块,求逆器采用查表方法.采用以上方法的组合,使得在资源占用允许的同时最大限度地提高了编解码速度.
|
| 关 键 词： | 数字视频广播(DVB) RS编解码 现场可编程逻辑阵列(FPGA) BM算法 FPGA 编解码器 设计流程 based decoder encoder fast implementation 解码速度 资源占用 组合 查表方法 求逆 关键模块 算法实现 并行结构 编码器 乘法器 自上而下 |
Design and implementation of fast RS encoder and decoder based on FPGA |
| |
| GU Yan-li,ZHOU Hong-min.Design and implementation of fast RS encoder and decoder based on FPGA[J].Information Technology,2008,32(6). |
| |
| Authors: | GU Yan-li ZHOU Hong-min |
| |
| Institution: | GU Yan-li,ZHOU Hong-min(College of Optoelectronic Engineering,Nanjing University of Posts , Telecommunications,Nanjing 210003,China) |
| |
| Abstract: | In this paper,the design of RS(255,191) encoder and decoder is mainly introduced.According to top-down design flow FPGA implementation of this algorithm is given.The multiplier in GF(28) was realized by different ways according to their different characteristics.The encoder is designed using parallel structure,the decoder is designed using parallel-inversionless BM algorithm to implement its key module,a look-up table method is adopted to implement inversion.Using a combination of the above methods the pape... |
| |
| Keywords: | Digital Video Broadcasting(DVB) RS encoding and decoding Field Programmable Gate Array(FPGA) BM algorithm |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
