首页 | 本学科首页   官方微博 | 高级检索  
     检索      

低相噪硅雷达射频频率源的研究与设计
引用本文:李旺,唐俊.低相噪硅雷达射频频率源的研究与设计[J].固体电子学研究与进展,2012,32(6):575-578.
作者姓名:李旺  唐俊
作者单位:成都国腾电子技术股份有限公司,成都,610041
摘    要:分析了频率源中各个模块的噪声传递函数,确定影响近端噪声的模块分别是鉴频鉴相器-电荷泵(PFD-CP)、分频器;在默认分频器相位噪声为-158dBc/Hz,通过matlab建模推断,需要PFD-CP模块在10kHz频偏处的输入噪声达到-143dBc/Hz,才能实现频率源输出信号在10kHz频偏处相位噪声-107dBc/Hz。采用0.18μmSiGe BiCMOS工艺,设计了整块芯片,着重优化了PFD-CP模块的输入噪声,经过spectre仿真,PFD-CP模块的输入噪声为-146dBc/Hz,经过实测,输出信号在10kHz频偏处相位噪声为-108dBc/Hz,达到设计预期。

关 键 词:频率源  鉴频鉴相器  分频器  电荷泵  相位噪声

Research and Design of the Low Phase Noise Frequency Synthesizer with Integrated VCO
LI Wang , TANG Jun.Research and Design of the Low Phase Noise Frequency Synthesizer with Integrated VCO[J].Research & Progress of Solid State Electronics,2012,32(6):575-578.
Authors:LI Wang  TANG Jun
Institution:(Chengdu Goldtel Electronic Technology CO.,LTD,Chengdu,610041,CHN)
Abstract:Based on analysis of the phase noise model of the frequency synthesizer,it is known that the PFD-CP(phase frequency detector and charge pump) noise and the divider noise are the main contributer of the phase noise.By using matlab model if the divider phase noise of-158 dBc/Hz,is default value PFD-CP must attain-143 dBc/Hz at 10 kHz offset in order to realize the designed synthesizer phase noise of-107 dBc/Hz.The frequency synthesizer chip has been designed in 0.18 μm SiGe BiCMOS technology,simulated results by spectre show that charge pump noise is-146 dBc/Hz at 10 kHz.Measured phase noise of the frequency synthesizer is-108 dBc/Hz@10 kHz at 3 GHz.
Keywords:frequency synthesizer  PFD-CP  divider  charge pump  phase noise
本文献已被 CNKI 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号