| Viterbi译码算法Soft Core IP的低功耗设计 |
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| 引用本文： | 乔锋,陈进,傅宇卓. Viterbi译码算法Soft Core IP的低功耗设计[J]. 通信技术, 2003, 0(9): 22-24 |
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| 作者姓名： | 乔锋 陈进 傅宇卓 |
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| 作者单位： | 上海交通大学芯片与系统研究中心,上海,200030 |
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| 基金项目： | 国家863项目资助(2002AA1Z1120)。 |
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| 摘 要： | 介绍了Viterbi译码算法SoftCoreIP的一种低功耗实现方案,对其中的核心功能单元ACS(Adder_Compare_Select)提出了一种改进的设计结构,并介绍了电路时钟的优化技术及低功耗设计技术,经实验证明,确实达到了降低功耗、减小电路规模的设计目的。
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| 关 键 词： | Viterbi IP 加比选 低功耗设计 |
| 修稿时间： | 2003-02-24 |
Low Power Design for Soft Core IP of Viterbi Algorithm |
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| Qiao Feng Chen Jin Fu Yuzhuo. Low Power Design for Soft Core IP of Viterbi Algorithm[J]. Communications Technology, 2003, 0(9): 22-24 |
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| Authors: | Qiao Feng Chen Jin Fu Yuzhuo |
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| Abstract: | A low power implementation of viterbi Soft Core Intellectual Property is introduced here,through which an improved architecture of Add-Compare-Selece function cell, the core of viterbi decoding system is proposed. Also the optimization on clock and low power design technique is described. The experiment results show that this method can surely reduce power dissipation and diminish circuit size. |
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| Keywords: | Viterbi IP add-compare-select low power design |
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