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5G 功放DPD 的FPGA 宽带实现及自动优化
引用本文:苗德华,刘太君,胡克佳,叶,焱,许高明.5G 功放DPD 的FPGA 宽带实现及自动优化[J].微波学报,2022,38(6):61-66.
作者姓名:苗德华  刘太君  胡克佳      许高明
作者单位:1. 宁波大学 信息科学与工程学院,宁波 315211; 2. 西北工业大学宁波研究院,宁波 315048
摘    要:5G 宽带功放数字预失真器(DPD)的FPGA 实现过程中,常遇到数字处理带宽不够和资源有限问题,对 此,文中提出一种基于双路并行数据流的数字预失真带宽扩展方法和基于Zynq Ultrascale+ MPSoC 的自动化模型优化 验证方法,可快速实现对5G 宽带功放线性化方案的优化。使用该并行处理结构的数字预失真器,克服了数字电路最 大时钟频率造成的对FPGA 线性化带宽的限制,使得数字预失真电路在每个时钟周期内可以处理更多的数据,不仅有 效地增加了数字处理带宽,而且降低了DPD 的功耗。然而,这种带宽增加以消耗更多硬件资源为代价,对此,文中同时 提出了对预失真非线性模型的在线自动优化方法,以简化非线性模型、降低DPD 的硬件资源开销。最后,在Zynq Ultrascale+ FPGA 实验平台上实现了具有两路并行数据处理的I-MSA 自优化数字预失真电路,采用100 MHz 的5G 新无 线电(NR)信号在2. 6 GHz 功率放大器上进行线性化实验验证,获得了满意的预失真性能,验证了所提方法的有效性。

关 键 词:5G  功放  数字预失真器  预失真  线性化  现场可编程门阵列

FPGA Wideband Implementation and Automatic Optimization of DPD for 5G Power Amplifiers
MIAO De-hu,LIU Tai-jun,HU Ke-ji,YE Yan,XU Gao-ming.FPGA Wideband Implementation and Automatic Optimization of DPD for 5G Power Amplifiers[J].Journal of Microwaves,2022,38(6):61-66.
Authors:MIAO De-hu  LIU Tai-jun  HU Ke-ji  YE Yan  XU Gao-ming
Institution:1. College of Information Science and Engineering, Ningbo University, Ningbo 315211, China; 2. Ningbo Research Institute of Northwestern Polytechnical University, Ningbo 315048, China
Abstract:To solve the problems of insufficient digital processing bandwidth and limited resources encountered in the FPGA implementation of digital predistorter (DPD) for 5G broadband power amplifier, this paper proposes a digital predistortion bandwidth extension method based on dual parallel data streams and Zynq Ultrascale+ MPSoC automatic model optimization verification method. It can quickly realize the optimization of the 5G broadband power amplifier linearization scheme. The digital predistorter using the parallel processing structure overcomes the limitation of FPGA linearization bandwidth caused by the maximum clock frequency of the digital circuit, so that the digital predistortion circuit can process more data in each clock cycle, not only effectively increasing the digital processing bandwidth, but also reducing the power consumption of the DPD. However, this increase in bandwidth is at the expense of more hardware resources. Therefore, an online automatic optimization method for the predistortion nonlinear model is also proposed to simplify the nonlinear model and reduce the hardware resource of the DPD. Finally, an I-MSA self-optimizing digital predistortion circuit with 2-channel parallel data processing is implemented on the Zynq Ultrascale+ FPGA experimental platform. A 100 MHz 5G NR signal is used for linearization experiment verification on a 2. 6 GHz power amplifier, and a satisfactory prediction is obtained. The distortion performance verifies the effectiveness of the proposed method.
Keywords:5G power amplifier  digital predistorter (DPD)  predistortion  linearization  field programmable gate array (FPGA)
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