A 14-bit dual-path 2-0 MASH ADC with dual digital error correction |
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| Authors: | Zhenyong Zhang Jesper Steensgaard Gabor C Temes Jian-yi Wu |
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| Institution: | (1) National Semiconductor, 2900 Semiconductor Drive, Mail Stop E3140, Santa Clara, CA 95051, USA;(2) School of EECS, Oregon State University, Corvallis, OR, USA;(3) Linear Technology, Milpitas, CA, USA |
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| Abstract: | A dual-path 2-0 cascaded delta-sigma (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch
errors. The digital correction techniques greatly reduced the requirements on the analog circuits. The dual-path structure
allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB
dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18 μm process. |
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