A 1.0-GHz single-issue 64-bit powerPC integer processor |
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| Authors: | Silberman J Aoki N Boerstler D Burns JL Sang Dhong Essbaum A Ghoshal U Heidel D Hofstee P Kyung Tek Lee Meltzer D Hung Ngo Nowka K Posluszny S Takahashi O Vo I Zoric B |
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| Institution: | IBM Thomas J. Watson Res. Center, Yorktown Heights, NY; |
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| Abstract: | The organization and circuit design of a 1.0 GHz integer processor built in 0.25 μm CMOS technology are presented, a microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented |
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