基于FPGA的IRIG-B码解码器设计

针对基于单片机的IRIG-B码解码器解码精度低、工作稳定性差等问题,提出了一种基于FPGA的IRIG-B码解码器设计。在实现过程中着重分析了输入IRIG-B码信号的毛刺问题,并采用三级D触发器后接或门的方法,彻底消除毛刺对本系统稳定性的影响。通过仿真验证了本系统具有解码精度高、工作稳定性强、易于实现等优点。

Design of an IRIG-B Decoder Based on FPGA

To solve the problem of low decoding accuracy and poor working stability of an IRIG B decoder based on the single chip microcomputer,this paper describes an IRIG B decoding hardware implementation based on FPGA.In the process of implementation,emphasis is put on analyzing and processing burrs introduced by the IRIG B code signal.The influence on the stability of the system caused by burrs is thoroughly eliminated by the method of three level D flip flop followed by OR gate.This system has the advantages of higher decoding precision,stability and easy implementation.