Effect of post-deposition annealing temperature on RF-sputtered HfO2 thin film for advanced CMOS technology |
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| Affiliation: | 1. University of Florida, Department of Electrical and Computer Engineering, Gainesville, Florida, 32611, USA;2. University of Florida, Department of Materials Science and Engineering, Gainesville, Florida, 32611, USA;3. University of Florida, Department of Mechanical and Aerospace Engineering, Gainesville, Florida, 3261, USA;1. Department of Applied Materials and Optoelectronic Engineering, National Chi Nan University, Puli, Nantou Hsien 54561, Taiwan, R.O.C.;2. Department of Electrical Engineering, National Chi Nan University, Puli, Nantou Hsien 54561, Taiwan, R.O.C.;1. Shibaura Institute of Technology, 3-7-5 Toyosu, Koto-ku, Tokyo 135-8548, Japan;2. International Center for Materials Nanoarchitectonics (WPI-MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan;3. National Institute for Materials Science, 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan;4. Joining and Welding Research Institute, Osaka University, 11-1, Mihogaoka, Ibaraki, Osaka 567-0047, Japan |
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| Abstract: | Structural and electrical properties of HfO2 gate-dielectric metal-oxide-semiconductor (MOS) capacitors deposited by sputtering are investigated. The HfO2 high-k thin films have been deposited on p-type <100> silicon wafer using RF-Magnetron sputtering technique. The Ellipsometric, FTIR and AFM characterizations have been done. The thickness of the as deposited film is measured to be 35.38 nm. Post deposition annealing in N2 ambient is carried out at 350, 550, 750 °C. The chemical bonding and surface morphology of the film is verified using FTIR and AFM respectively. The structural characterization confirmed that the thin film was free of physical defects and root mean square surface roughness decreased as the annealing temperature increased. The smooth surface HfO2 thin films were used for Al/HfO2/p-Si MOS structures fabrication. The fabricated Al/HfO2/p-Si structure had been used for extracting electrical properties such as dielectric constant, EOT, interface trap density and leakage current density through capacitance voltage and current voltage measurements. The interface state density extracted from the G–V measurement using Hill Coleman method. Sample annealed at 750 °C showed the lowest interface trap density (3.48 × 1011 eV−1 cm−2), effective oxide charge (1.33 × 1012 cm−2) and low leakage current density (3.39 × 10−9 A cm−2) at 1.5 V. |
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