The delay of circuits whose inputs have specified arrival times |
| |
Authors: | Dieter Rautenbach Christian Szegedy |
| |
Institution: | a Institut für Mathematik, TU Ilmenau, Postfach 100565, D-98684 Ilmenau, Germany b Cadence Berkeley Labs, 1995 University Ave, Berkeley, CA 94704, USA c Forschungsinstitut für Diskrete Mathematik, Lennéstr. 2, D-53113 Bonn, Germany |
| |
Abstract: | Let C be a circuit representing a straight-line program on n inputs x1,x2,…,xn. If for 1?i?n an arrival timeti∈N0 for xi is given, we define the delay of xi in C as the sum of ti and the maximum number of gates on a directed path in C starting in xi. The delay of C is defined as the maximum delay of one of its inputs.The notion of delay is a natural generalization of the notion of depth. It is of practical interest because it corresponds exactly to the static timing analysis used throughout the industry for the analysis of the timing behaviour of a chip. We prove a lower bound on the delay and construct circuits of close-to-optimal delay for several classes of functions. We describe circuits solving the prefix problem on n inputs that are of essentially optimal delay and of size O(nlog(logn)). Finally, we relate delay to formula size. |
| |
Keywords: | Circuit Straight-line program Depth Size Prefix problem Computer arithmetic VLSI design Static timing analysis |
本文献已被 ScienceDirect 等数据库收录! |
|