A super-junction SOI-LDMOS with low resistance electron channel

A novel super-junction LDMOS with low resistance channel (LRC), named LRC-LDMOS based on the silicon-on-insulator (SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance (R_on,sp) in forward conduction. The charge compensation between the LRC, N-pillar, and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift, thus the breakdown voltage (BV) is enhanced in reverse blocking. The three-dimensional (3D) simulation results show that the BV and R_on,sp of the device can reach 253 V and 15.5 mΩ·cm², respectively, and the Baliga's figure of merit (FOM=BV²/R_on,sp) of 4.1 MW/cm² is achieved, breaking through the silicon limit.