一种基于三维可变换CNN加速结构的并行度优化搜索算法

现场可编程门阵列(FPGA)被广泛应用于卷积神经网络(CNN)的硬件加速中。为优化加速器性能，Qu等人(2021)提出了一种3维可变换的CNN加速结构，但该结构使得并行度探索空间爆炸增长，搜索最优并行度的时间开销激增，严重降低了加速器实现的可行性。为此该文提出一种细粒度迭代优化的并行度搜索算法，该算法通过多轮迭代的数据筛选，高效地排除冗余的并行度方案，压缩了超过99%的搜索空间。同时算法采用剪枝操作删减无效的计算分支，成功地将计算所需时长从106 h量级减少到10 s内。该算法可适用于不同规格型号的FPGA芯片，其搜索得到的最优并行度方案性能突出，可在不同芯片上实现平均(R1, R2)达(0.957, 0.962)的卓越计算资源利用率。

A Parallelism Strategy Optimization Search Algorithm Based on Three-dimensional Deformable CNN Acceleration Architecture

Field Programmable Gate Array (FPGA) is widely used in Convolutional Neural Network (CNN) hardware acceleration. For better performance, a three-dimensional transformable CNN acceleration structure is proposed by Qu et al (2021). However, this structure brings an explosive growth of the parallelism strategy exploration space, thus the time cost to search the optimal parallelism has surged, which reduces severely the feasibility of accelerator implementation. To solve this issue, a fine-grained iterative optimization parallelism search algorithm is proposed in this paper. The algorithm uses multiple rounds of iterative data filtering to eliminate efficiently the redundant parallelism schemes, compressing more than 99% of the search space. At the same time, the algorithm uses pruning operation to delete invalid calculation branches, and reduces successfully the calculation time from 106 h to less than 10 s. The algorithm can achieve outstanding performance in different kinds of FPGAs, with an average computing resource utilization (R1, R2) up to (0.957, 0.962).