堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.

Two-dimensional model of symmetrical double-gate strained Si single Halo metal-oxide semiconductor field effect transistor with gate stack dielectric

In this paper, a novel symmetrical double-gate strained Si single halo metal-oxide semiconductor field effect transistor with gate stack dielectric is proposed. The two-dimensional Poisson's equation is solved under suitable boundary condition by applying the parabolic potential approximation. This analytical model for the surface potential and the threshold voltage is derived. The strained Si channel is divided into two different doping regions, and the surface potential along the channel, compared with the normal double-gate device (uniform doping channel), exhibits a stepped potential variation, which can increase carrier transport speed. The influence of drain-source voltage on short channel effects (SCEs) is discussed. it is shown that threshold voltage decreases with Ge mole fraction increasing in butter layer, increases with the increase of the high-k layer dielectric permittivity of gate stack, and increases with the increase of doping concentration in the channel near the source, of which the physical mechanisms are analyzed and explained. Results show that the novel device can suppress threshold voltage drift and SCEs, which provides the basic guidance for designing the CMOS-based devices in nanometer scale.
Keywords： strained Si single halo symmetrical double-gate metal-oxide semiconductor field effect transistor