Design trade-offs in optoelectronic parallel processing systems using smart-SLMs

Optoelectronic devices with free-space optical interconnections offer new possibilities in massively parallel processing. The trade-offs involved in system design and device selection for optoelectronic implementations are examined. System design trade-offs are approached from algorithmic and technological standpoints. From the algorithmic standpoint, new architectures based on expander graphs, that have been shown to provide low-contention fault-tolerant communication, are discussed. Optoelectronic systems which implement such random graphs can be folded to reduce the hardware cost or unfolded to increase bandwidth. They can also be partially folded by increasing the grain size or by reducing the randomness of the graph topology to reduce the complexity of the interconnection holograms. An optoelectronic and a VLSI implementation of a multistage interconnection network are compared from a technological standpoint. Physical design parameters, such as the chip size or the number of phase levels of the interconnection holograms, are related to the system design metrics such as bandwidth, volume, area and power. It is shown that the optoelectronic implementations have higher performance and are more cost-effective than VLSI implementations. These results are also used to provide general guidelines for device selection in the design of smart pixels/smart spatial light modulators based optoelectronic systems.