| Abstract: | In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply‐scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on‐chip pseudorandom generator composed of an address‐based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x‐nm and 4x‐nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage. |
