基于DCVSPG逻辑的双轨四相异步电路设计

基于四相双轨异步电路设计的芯片面积较单轨异步电路成倍增大,提出了将异步DCVSPG(ADCVSPG)逻辑用于双轨四相异步电路设计.为了适应异步电路设计,在ADCVSPG逻辑单元电路的互补输出端,由一个与非门来实现完成判断电路,同时在每个互补输出端分别添加一个由反向器构成的锁存器,以此提高电路的稳定性,并使得ADCVSPG适合于异步细粒度流水线设计.在HSPICE下对ADCVSPG逻辑和零协议逻辑(Null Convention Logic,NCL)进行了分析.分析表明,ADCVSPG逻辑提高了双轨四相异步电路的性能,减小了芯片面积,是一种较佳的设计方法.

Dual-Rail Four-Phase Asynchronous Circuit Design Based on DCVSPG Logic

The area of the asynchronous circuit designed by the duai-rail four-phase handshake protocol is almost twice of that designed by the single-rail circuit. An asynchronous differential cascode voltage switch with pass-gate (ADCVSPG) logic was proposed to alleviate this problem. A NAND gate is used as completion detection circuit at the complementry output of the ADCVSPG cell. A latch composed of two converters is also added at each complementary output to improve the stability of the circuit and make ADCVSPG logic suitable for asynchronous fine-grain pipeline design. The paper analyzed both the ADCVSPG logic and Null Convention Logic (NCL) by HSPICE, and the results indicate that the circuit designed by ADCVSPG logic has better performance and smaller area.