注入势垒单相埋沟高速CCD延迟线设计

采用注入势垒单相埋沟结构和两层多晶硅一层铝工艺技术,研制出512位高速CCD延迟线,获得了大于10 MHz的工作频率和大于50 dB的动态范围。器件电极设计为准1相两层多晶硅交迭栅结构,信道设计为埋沟结构。输入结构采用双输入栅表面势平衡注入技术,输出结构采用浮置扩散源跟随放大器技术。提出了改善转移效率、暗电流、时钟频率和动态范围的有效方法。测试结果表明,器件性能参数达到设计要求。

Design of Implanted-Barrier Single-Phase Buried-Channel High-Speed CCD Delay Line

A 512-bit high-speed CCD delay line with operating frequency greater than 10 MHz and dynamic range over 50 dB was fabricated using implanted-barrier single-phase buried-channel structure and 2-polysilicon 1-aluminum processing technology.Electrodes of quasi-single-phase 2-polysilicon-layer overlapping-gate structure were designed for the device,and buried structure was used for channel.The input structure was achieved by double-input gate surface potential balanced injection,and floating diffusion source fo...